Integrated injection logic (I.sup.2 L), also called merged transistor logic (MTL), is fast becoming a major digital circuit technology due to its high packing density and very low power dissipation. However, until now I.sup.2 L circuits have achieved only medium speed operation (gate delays greater than 10 nanoseconds).
It is the principal object of the present invention to improve the basic I.sup.2 L structure to permit it to challenge high speed technologies such as the Schottky TTL while retaining its advantage of very low power operation.
In accordance with one feature of the present invention the doping profile of the vertical I.sup.2 L transistor is optimized by auto-doping into an epitaxial layer on a semiconductor substrate to form the base of the vertical transistor in that layer, with the doping concentration of the base being greater than that of the collector but smaller than that of the emitter of the transistor.
In accordance with another feature of the invention, the speed of the device is further enhanced by the formation of one or more Schottky diodes as integral parts of the I.sup.2 L structure.